09 Décembre – Thesis defense - David Cordova
10 h30 Amphi Jean-Paul Dom - Laboratory IMS / Building A31 (Talence campus)
Study and realization of a data conversion chain for very high speed digital links.
The increasing demand of higher data rates in datacenters has led to
new emerging standards (100 - 400G Ethernet and others) in wireline communications. These standards will favor more sophisticated encodings that use less frequency bandwidth. As speed requirements become more stringent, pure analog architectures can not meet them. So, a natural shift towards mixed-signal architectures is expected.
This thesis proposes the design of an ADC-based receiver architecture. It uses a design methodology to define and validate the requirements and specifications for silicon-based wireline receivers that comply with >100Gb/s operation over transmission channels with high losses (>20dB). A prototype in 22nm CMOS FDSOI technology is proposed as proof of concept.