30 Mars – Thesis defense - David Gaidioz

16 h In videoconference

UTBB technology for ultra-low power synthétiser and its application to the Internet of Things.

More than twenty billion of connected devices are predicted in the coming years. Considering a world population around eight billion people, it represents an average of three connected devices per person. This value is far from reality due to the unequal access to these technologies. However, the Internet-of-Things (IoT) is a common reality of our day-to-day lives. Concerning a connected object, two critical parameters have to be taken into account: the power consumption has to be minimized to increase the battery-operate lifetime, and the cost of the object has to be as low as possible to ensure a successful mass deployment.
Sub-system of any transceiver, the frequency synthesis design is ruled by the same IoT challenges. Although today solutions provide a power consumption around ten mW, Ultra Lower Power (ULP) solutions are more and more targeted. This virtuous goal brings the emergence of new innovative solutions. Realized in the frame of the common laboratory between STMicroelectronics and IMS Laboratory, this CIFRE thesis is targeting the following goals:
-    Highlight the limitations of the actual frequency synthesizer architectures dedicated to IoT applications. From this study, the possible improvements are determined to address the IoT challenges.
-    Propose a new frequency synthesis circuit implemented in 28nm FD-SOI technology. The specifications of this alternative solution are drawn to reach optimum compromise in terms of power consumption, RF performances and silicon area.
-    Support the ecosystem of the FD-SOI technology by using body-bias specific features. The proposed solution brings competitive advantages, only possible with the FD-SOI technology.

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