19 Novembre – Thesis defense - Joris Jourdon

14 h Amphi Jean-Paul Dom - laboratory IMS / building A31 (Talence campus)

Hybrid bonding for 3D integration: challenges of the pitch shrinkage.

With the beginning of the 4th industrial revolution and the Internet of Things, the number of integrated circuits in electronic devices increases. Since Moore’s law becomes harder to keep up with, 3D integration is an alternative to produce multi-function chips with small form factor. Hybrid bonding enables a highly robust wafer-to-wafer assembly with a density of 106 interconnects/cm2. For these reasons, this technology is of special interest for image sensors. A pitch reduction down to 1.44 µm would enable a density of interconnects fifty times higher and the design of more performant architectures. However, the effects of such modification on the bonding mechanism, electrical properties and the robustness of interconnects remain unknown.
This work aims to validate a Cu-SiO2 hybrid bonding integration with a pitch of 1.44 µm. For this study, electrical measurements and accelerated aging tests are performed on dedicated test vehicles with various pitches. A thorough morphological characterization of bonding pads with different sizes allowed the identification of voids and Cu2O nodules at Cu/Cu interface, which indicates a common bonding mechanism. A new method based on electrical measurements and finite element method simulation was developed in order to estimate contact resistivity. It appears that defects at Cu/Cu interface do not increase the resistance of interconnects. Test structures were specially designed to monitor copper diffusion at bonding interface by making compatible chemical and electrical analysis with hybrid bonding integration. Various conditions of bonding and passivation annealings were tested in order to lower the thermal budget of the bonding annealing and assure the compatibility of hybrid bonding process with the whole stack. The pitch limitation was determined thanks to the study of interconnect resistance sensitivity to wafer-to-wafer misalignment. This deep comprehension of effects related to pitch shrinkage and technological process will be valuable to create new architecture.

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