07 Octobre – Thesis defense - Julien Coutet

10 h30 Amphi Jean-Paul Dom - laboratory IMS / Building A31 (Talence campus)

Study of the reliability and mechanisms of degradation in DSM digital integrated circuits.

The downscaling of transistors in commercial electronic circuits has been permitted by the use of new materials in gate oxide (especially for DSM bound). In order to fully trust this kind of chips in extreme environments, it is necessary to make a proper reliability assessment. We choose two types of integrated circuits to carry this study: NAND flash memories and FPGA. Accelerated ageing has been applied to distinctly activate the various degradation mechanisms. Then results are analyzed and a precise statistical approach leads us to a realistic estimation of its reliability.
Our ageing tests of NAND flash memories showed that storage temperature as well as many program-erase cycles significantly decrease the retention time of data. Our method demonstrates that a wide gap between the temperature of writing and the temperature of reading leads to a meaningful lack of reliability in retention of data. This issue is not due to the physic of memory cells at low temperature but it is due to drifts of the peripheral management circuit (in charge of writing and reading operations). However we have confirmed this weak reliability is caused by MLC design and not by the technologic node. Error code correction, wear leveling or even over-provisioning allow sufficient reliability. Therefore they are an important part of global memory and must be taken in account in the reliability calculation.
Digital circuit ageing has been monitored by means of ring oscillators embedded in FPGA. We well measured some BTI and few HCI, but we did not succeed in involving any electromigration or TDDB. Drifts of both mechanisms are modeled. A new methodology based on the assumption of LUT design from patents is described and applied in order to extract degradations at transistor level: NBTI and PBTI can be set apart.. Moreover the analysis of small drifts occurred at low temperature which is evidence that HCI was involved. These low temperature degradations are correlated with the number of commutations. Finally, the estimation of reliability based on the sum of HCI and BTI failure rates gives false result.  We present a proper approach to estimate reliability. It considers the sum of both drifts until a user’s determined criterion of failure is reached.

Event localization