03 Juin – Thesis defense - Thi-Phuong-Yen Tran
10 h Amphi Jean-Paul Dom - laboratory IMS / Building A31 (University of Bordeaux - Talence campus)
CMOS 180 nm Compact Modeling Including Ageing Laws for Harsh Environment.
In the past decades, the demand for complicated functionality and high-density integration for Integrated Circuits (ICs) has resulted in metal-oxide-silicon (MOS) devices' scaling down. In this scenario, the reliability problems are the considerable concerns due to the device miniaturization, such as Hot Carrier Injection (HCI) and Bias Temperature Instability (BTI) that seriously impact the device performance. In some application fields where the cost of failure is extremely high such as space, oilfield, or healthcare, the device must be able to stably and reliably work, especially at an extensive temperature range. Although device failure mechanisms have been intensively investigated in the past, the investigations of these mechanisms at high temperatures are seldom studied.
This thesis aims to develop the aging laws for 0.18µm CMOS technology to optimize circuit design for a targeted lifetime under extreme temperatures. We conducted an intensive aging test campaign for both nMOS and pMOS featuring several gate lengths. The intrinsic HCI and BTI mechanisms were characterized and modeled under typical operating voltage biases to avoid the risk of overaccelerating other wear-out mechanisms that are not supposed to be experienced in practical application. Our experiment is a long-term test with a stress time of up to 2,000 hours. This thesis presents measurement results up to 230°C that have never been studied before in the literature for this technology.
The aging laws are finally integrated into an electronic design automation (EDA) environment to predict the evolution of the degraded transistor/circuit electrical parameters and the lifetime estimation due to the aging effects. In addition, the reliability test at the circuit level has been performed to validate and verify the proposed aging models. This approach offers the possibility to assess and simulate the IC specification drift due to the aging effect in the early design phase.