10 Juin – Thesis defense - Yann Delomier

14 h Amphi - Laboratory IMS (Talence campus)

Design and prototyping of error-correcting code decoders from behavioural models.

Digital communications are ubiquitous in the communicating objects of everyday life. Evolving communication standards, shorter time-to-market, and heterogeneous applications make the design for digital circuit more challenging. Fifth generation (5G) mobile technologies are an illustration of the current and future challenges. In this context, the design of digital architectures for the implementation of error-correcting code decoders will often turn out to be especially difficult. High Level Synthesis (HLS) is one of the computer-aided design (CAO) methodologies that facilitates the fast prototyping of digital architectures. This methodology is based on behavioral descriptions to generate hardware architectures. However, the design of efficient behavioral models is essential for the generation of high-performance architectures. The results presented in this thesis focus on the definition of efficient behavioral models for the generation of error-correcting code decoder architectures dedicated tp LDPC codes and polar codes. These two families of error-correcting codes are the ones adopted in the 5G standard. The proposed behavioural models have to combine flexibility, fast prototyping and efficiency.
A first significant contribution of the research thesis is the proposal of two behavioural models that enables the generation of efficient hardware architectures for the decoding of LDPC codes. These models are generic. They are associated with a flexible methodology. They make the space exploration of architectural solutions easier. Thus, a variety of trade-offs between throughput, latency and hardware complexity are obtained. Furthermore, this contribution represents a significant advance in the state of the art regarding the automatic generation of LDPC decoder architectures. Finally, the performances that are achieved by generated architectures are similar to that of handwritten architectures with an usual CAO methodology.
A second contribution of this research thesis is the proposal of a first behavioural model dedicated to the generation of hardware architectures of polar code decoders with a high-level synthesis methodology. This generic model also enables an efficient exploration of the architectural solution space. It should be noted that the performance of synthesized polar decoders is similar to that of state-of-the-art polar decoding architectures.
A third contribution of the research thesis concerns the definition of a polar decoder behavioural model that is based on a "list" algorithm, known as successive cancellation list decoding algorithm. This decoding algorithm enables to achieve higher decoding performance at the cost of a significant computational overhead. This additional cost can also be observed on the hardware complexity of the resulting decoding architecture. It should be emphasized that the proposed behavioural model is the first model for polar code decoders based on a "list" algorithm

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